Merge branch 'add_signed_regs' into 'master'

Add signed commands WeightValDFl/Sig

See merge request !5

include/Frelon.h

@@ -49,7 +49,7 @@ enum Reg {
 	SingleVertXfer,	SingleHorzXfer,	AllVertXfer,	AllHorzXfer,
 	ReadoutTime,	TransferTime,   CcdModesAvail,	StatusSeqA,
 	StatusAMTA,	StatusAMTB,	StatusAMTC,	StatusAMTD,
-	LookUpTable,	ImagesPerEOF,
+	LookUpTable,	ImagesPerEOF,	WeightValDFl,	WeightValSig,
 };
 
 typedef std::map<Reg, std::string> RegStrMapType;
@@ -58,6 +58,7 @@ extern RegStrMapType RegStrMap;
 typedef std::vector<Reg> RegListType;
 extern RegListType CacheableRegList;
 extern RegListType FloatRegList;
+extern RegListType SignedRegList;
 
 typedef std::map<Reg, double> RegDoubleMapType;
 extern RegDoubleMapType RegSleepMap;

include/FrelonSerialLine.h

@@ -37,7 +37,7 @@ class SerialLine : public HwSerialLine
 
  public:
 	enum MsgPart {
-		MsgSync, MsgCmd, MsgVal, MsgDec, MsgReq, MsgTerm, 
+		MsgSync, MsgCmd, MsgVal, MsgDec, MsgReq, MsgTerm, MsgSign,
 	};
 	
 	enum AnsPart {

sip/Frelon.sip

@@ -69,6 +69,7 @@ public:
 typedef std::vector<Reg> RegListType;
 extern RegListType CacheableRegList;
 extern RegListType FloatRegList;
+extern RegListType SignedRegList;
 
 typedef std::map<Reg, double> RegDoubleMapType;
 extern RegDoubleMapType RegSleepMap;

src/Frelon.cpp

@@ -95,6 +95,8 @@ static const RegPair RegStrCList[] = {
 
 	RegPair(LookUpTable,	"LUT"),
 	RegPair(ImagesPerEOF,	"NEF"),
+	RegPair(WeightValDFl,	"WVD"),
+	RegPair(WeightValSig,	"WVS"),
 };
 RegStrMapType lima::Frelon::RegStrMap(C_LIST_ITERS(RegStrCList));
 
@@ -114,6 +116,12 @@ static Reg FloatRegCList[] = {
 };
 RegListType lima::Frelon::FloatRegList(C_LIST_ITERS(FloatRegCList));
 
+static Reg SignedRegCList[] = {
+	WeightValDFl,
+	WeightValSig,
+};
+RegListType lima::Frelon::SignedRegList(C_LIST_ITERS(SignedRegCList));
+
 typedef pair<Reg, double> RegSleepPair;
 static const RegSleepPair RegSleepCList[] = {
 	RegSleepPair(ConfigHD,    2.0),

src/FrelonSerialLine.cpp

@@ -110,6 +110,19 @@ void SerialLine::writeCmd(const string& buffer, bool no_wait)
 			m_curr_reg = it->first;
 	}
 
+	bool has_sign = !msg_parts[MsgSign].empty();
+	if (has_sign) {
+		bool ok = false;
+		if (reg_found) {
+			const RegListType& list = SignedRegList;
+			RegListType::const_iterator end = list.end();
+			ok = (find(list.begin(), end, m_curr_reg) != end);
+		}
+		if (!ok)
+			THROW_HW_ERROR(InvalidValue)
+				<< "Command " << cmd << " cannot be negative";
+	}
+
 	m_curr_cache = false;
 	if (reg_found && isRegCacheable(m_curr_reg)) {
 		bool is_req = !msg_parts[MsgReq].empty();
@@ -409,7 +422,8 @@ void SerialLine::splitMsg(const string& msg,
 	const static RegEx re("^(?P<sync>>)?"
 			      "(?P<cmd>[A-Za-z]+)"
 			      "((?P<req>\\?)|"
-			      "(?P<val>[0-9]+(\\.(?P<dec>[0-9]+))?))?"
+			      "(?P<val>(?P<sign>-?)[0-9]+"
+			      "(\\.(?P<dec>[0-9]+))?))?"
 			      "(?P<term>[\r\n]+)?$");
 
 	RegEx::FullNameMatchType match;
@@ -422,6 +436,7 @@ void SerialLine::splitMsg(const string& msg,
 		KeyPair(MsgSync, "sync"), KeyPair(MsgCmd, "cmd"), 
 		KeyPair(MsgVal,  "val"),  KeyPair(MsgDec, "dec"),  
 		KeyPair(MsgReq,  "req"),  KeyPair(MsgTerm, "term"),
+		KeyPair(MsgSign, "sign"),
 	};
 	const KeyPair *it, *end = C_LIST_END(key_list);
 	for (it = key_list; it != end; ++it) {
@@ -431,8 +446,8 @@ void SerialLine::splitMsg(const string& msg,
 	}
 
 	DEB_RETURN() << DEB_VAR2(msg_parts[MsgSync], msg_parts[MsgCmd]);
-	DEB_RETURN() << DEB_VAR3(msg_parts[MsgReq], msg_parts[MsgVal],
-				 msg_parts[MsgDec]);
+	DEB_RETURN() << DEB_VAR4(msg_parts[MsgReq], msg_parts[MsgSign],
+				 msg_parts[MsgVal], msg_parts[MsgDec]);
 }
 
 void SerialLine::decodeFmtResp(const string& ans, string& fmt_resp)