1. 01 Dec, 2021 3 commits
  2. 15 Sep, 2021 2 commits
  3. 10 May, 2021 1 commit
  4. 11 Mar, 2021 4 commits
  5. 25 Feb, 2021 7 commits
    • David Schimansky's avatar
      In analysis: · 5a4daef4
      David Schimansky authored
      - Change plotSingle script to be able to plot T3 data (new data structure)
      5a4daef4
    • David Schimansky's avatar
      In software: · e88e9707
      David Schimansky authored
      - Rewrite measurement functions for new data structure of T3 (wip)
      e88e9707
    • David Schimansky's avatar
      In software: · 26a918c0
      David Schimansky authored
      - Fix T3 default config comparator threshold values back to correct values
      26a918c0
    • David Schimansky's avatar
      In software: · 8a6a6837
      David Schimansky authored
      - Add info messages to configuration process of sent pattern to ASIC
      8a6a6837
    • David Schimansky's avatar
      In firmware: · 1f9a6862
      David Schimansky authored
      - Add get_ebone_signal_names function to return array of signal names in ebone wrapper registers of ebone device.
      - Add hex value to printout of ebone wrapper register values
      1f9a6862
    • David Schimansky's avatar
      In manual: · 5d7bd368
      David Schimansky authored
      - Fix error in mon_sel bits
      5d7bd368
    • David Schimansky's avatar
      In manual: · ae0629d2
      David Schimansky authored
      - Fix error in mon_sel bits
      ae0629d2
  6. 23 Feb, 2021 1 commit
  7. 22 Feb, 2021 6 commits
    • David Schimansky's avatar
      In software: · 794d9750
      David Schimansky authored
      - Update default SUS65T3 config to correctly list conversion signals (gain, LSB correction, ...)
      - Set default value of gain to "3" which corresponds to a gain stage of 8.
      794d9750
    • David Schimansky's avatar
      In software: · cc5fb4ae
      David Schimansky authored
      - Update daq reset function to utilize new dedicated DAQ FIFO reset.
      cc5fb4ae
    • David Schimansky's avatar
      In software: · e11f507e
      David Schimansky authored
      - Add software counterpart for new T3Controller input register that allows controlling if sync word should be written to DAQ FIFO or not.
      - Set cmd_in_pattern_length of standard patterns to 50. Because the word clock is half the sequencer slow clock, this causes the sequencer and the T3 readout link to be in sync.
      e11f507e
    • David Schimansky's avatar
      In firmware: · 61fb8f00
      David Schimansky authored
      - Add extra reset for DAQ FIFO. This allows resetting the FIFO without having to reset the whole system at once.
      61fb8f00
    • David Schimansky's avatar
      In firmware: · 71742761
      David Schimansky authored
      - Rewrite fifo write enable logic in push_receiver in an attempt to fix the FIFO being filled after starting the readout with "sus_daq_print_read" when magic pattern is activated. To no effect..
      71742761
    • David Schimansky's avatar
      In firmware: · 84ac24cb
      David Schimansky authored
      - Add input for T3Controller to set if sync word should be written to DAQ FIFO or not
      - Add ebone register to control this new input
      84ac24cb
  8. 19 Feb, 2021 10 commits
    • David Schimansky's avatar
      In firmware: · f4ab3299
      David Schimansky authored
      - Add packer_16_to_64 as source file to Vivado project
      f4ab3299
    • David Schimansky's avatar
      In firmware: · d00e47ea
      David Schimansky authored
      - Encapsulate 16-to-64bit interface between dynamic asic control and daq fifo
      - Clean up sus_top and dblock_dmak_top
      d00e47ea
    • David Schimansky's avatar
      In firmware: · 6f50e8e8
      David Schimansky authored
      - Rearrange file structure for source files
      - Change Vivado project accordingly
      6f50e8e8
    • David Schimansky's avatar
      In firmware: · 5518c9a1
      David Schimansky authored
      - Update Vivado project for firmware compilation by adding new sources of Michael's code and updating paths
      5518c9a1
    • David Schimansky's avatar
      In software: · 5d09cdfc
      David Schimansky authored
      - Add configuration for test of new T3 link (difference to default config: en_pixel_control = 1, conversion = 32 ( => LSB_correction = 1))
      5d09cdfc
    • David Schimansky's avatar
      In binaries: · 420cd30f
      David Schimansky authored
      - Split bitfile upload script into suspc43 and suspc38 scripts
      420cd30f
    • David Schimansky's avatar
      In software: · ae669848
      David Schimansky authored
      - Add new EboneDevice child t3cont to control new registers of T3 control block with 8b10b output data link:
      	- Implement software counterparts of cmd_in_pattern_registers
      	- Add initialization function for 8b10b link
      	- Add functions to program preset telegram patterns (idle, magic, sync_idle)
      - Fix bug in dynamic ASIC control ebone register class. o_next_state address was wrong.
      - Update print_ebone_wrapper_regs function in EboneDevice class to also display register contents in hex.
      - Add get_ebone_signal_names function to EboneDevice to get names of ebone signals used by this device
      - Add show_gui function to DintefCmd class
      ae669848
    • David Schimansky's avatar
      Add clock generator simulation · 5d81078e
      David Schimansky authored
      5d81078e
    • David Schimansky's avatar
    • David Schimansky's avatar
      In DMAK firmware: · 4e217f58
      David Schimansky authored
      - Add Michael's T3 controller
      - Add debug pins to T3 controller (phase finder state, clockgen all locked)
      - Add ebone registers for:
      	- Telegram pattern
      	- Link initialization
      	- Link status (Link detected)
      	- Debug pins
      - Replace dyn_data_out_valid of old data link with FIFO_WEN of new link
      - Replace write clock of FIFO with FIFO_WCLK of new link
      - Rewire LA4_P/N pads of FPGA to T3 DATA_FROM_ASIC (input coming from T3) instead of ser0 (input coming from T2)
      - Rewire LA7_P/N pads of FPGA to T3 cmd in (output going to T3) instead of ser1 (input coming from T2)
      - Add active high reset ( = not active low reset )
      - Change monitor TPs to show FIFO_WEN and FIFO_WCLK
      - Change PATTERN pin of T3Controller to 582 vector to tunnel pattern_t struct through vhdl top hierarchy
      4e217f58
  9. 26 Nov, 2020 3 commits
  10. 16 Nov, 2020 1 commit
  11. 04 Nov, 2020 2 commits