- 01 Dec, 2021 3 commits
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David Schimansky authored
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David Schimansky authored
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David Schimansky authored
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- 15 Sep, 2021 2 commits
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David Schimansky authored
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David Schimansky authored
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- 10 May, 2021 1 commit
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David Schimansky authored
Change frequency constraint of ASIC data output link to 500MHz. With this setting the FPGA manages to initialize stable 500MHz links with the ASIC
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- 11 Mar, 2021 4 commits
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David Schimansky authored
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David Schimansky authored
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David Schimansky authored
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David Schimansky authored
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- 25 Feb, 2021 7 commits
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David Schimansky authored
- Change plotSingle script to be able to plot T3 data (new data structure)
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David Schimansky authored
- Rewrite measurement functions for new data structure of T3 (wip)
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David Schimansky authored
- Fix T3 default config comparator threshold values back to correct values
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David Schimansky authored
- Add info messages to configuration process of sent pattern to ASIC
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David Schimansky authored
- Add get_ebone_signal_names function to return array of signal names in ebone wrapper registers of ebone device. - Add hex value to printout of ebone wrapper register values
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David Schimansky authored
- Fix error in mon_sel bits
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David Schimansky authored
- Fix error in mon_sel bits
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- 23 Feb, 2021 1 commit
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Manuel Perez authored
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- 22 Feb, 2021 6 commits
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David Schimansky authored
- Update default SUS65T3 config to correctly list conversion signals (gain, LSB correction, ...) - Set default value of gain to "3" which corresponds to a gain stage of 8.
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David Schimansky authored
- Update daq reset function to utilize new dedicated DAQ FIFO reset.
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David Schimansky authored
- Add software counterpart for new T3Controller input register that allows controlling if sync word should be written to DAQ FIFO or not. - Set cmd_in_pattern_length of standard patterns to 50. Because the word clock is half the sequencer slow clock, this causes the sequencer and the T3 readout link to be in sync.
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David Schimansky authored
- Add extra reset for DAQ FIFO. This allows resetting the FIFO without having to reset the whole system at once.
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David Schimansky authored
- Rewrite fifo write enable logic in push_receiver in an attempt to fix the FIFO being filled after starting the readout with "sus_daq_print_read" when magic pattern is activated. To no effect..
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David Schimansky authored
- Add input for T3Controller to set if sync word should be written to DAQ FIFO or not - Add ebone register to control this new input
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- 19 Feb, 2021 10 commits
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David Schimansky authored
- Add packer_16_to_64 as source file to Vivado project
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David Schimansky authored
- Encapsulate 16-to-64bit interface between dynamic asic control and daq fifo - Clean up sus_top and dblock_dmak_top
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David Schimansky authored
- Rearrange file structure for source files - Change Vivado project accordingly
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David Schimansky authored
- Update Vivado project for firmware compilation by adding new sources of Michael's code and updating paths
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David Schimansky authored
- Add configuration for test of new T3 link (difference to default config: en_pixel_control = 1, conversion = 32 ( => LSB_correction = 1))
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David Schimansky authored
- Split bitfile upload script into suspc43 and suspc38 scripts
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David Schimansky authored
- Add new EboneDevice child t3cont to control new registers of T3 control block with 8b10b output data link: - Implement software counterparts of cmd_in_pattern_registers - Add initialization function for 8b10b link - Add functions to program preset telegram patterns (idle, magic, sync_idle) - Fix bug in dynamic ASIC control ebone register class. o_next_state address was wrong. - Update print_ebone_wrapper_regs function in EboneDevice class to also display register contents in hex. - Add get_ebone_signal_names function to EboneDevice to get names of ebone signals used by this device - Add show_gui function to DintefCmd class
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David Schimansky authored
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David Schimansky authored
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David Schimansky authored
- Add Michael's T3 controller - Add debug pins to T3 controller (phase finder state, clockgen all locked) - Add ebone registers for: - Telegram pattern - Link initialization - Link status (Link detected) - Debug pins - Replace dyn_data_out_valid of old data link with FIFO_WEN of new link - Replace write clock of FIFO with FIFO_WCLK of new link - Rewire LA4_P/N pads of FPGA to T3 DATA_FROM_ASIC (input coming from T3) instead of ser0 (input coming from T2) - Rewire LA7_P/N pads of FPGA to T3 cmd in (output going to T3) instead of ser1 (input coming from T2) - Add active high reset ( = not active low reset ) - Change monitor TPs to show FIFO_WEN and FIFO_WCLK - Change PATTERN pin of T3Controller to 582 vector to tunnel pattern_t struct through vhdl top hierarchy
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- 26 Nov, 2020 3 commits
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David Schimansky authored
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David Schimansky authored
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David Schimansky authored
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- 16 Nov, 2020 1 commit
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David Schimansky authored
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- 04 Nov, 2020 2 commits
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David Schimansky authored
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David Schimansky authored
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