Commit 77b00810 authored by Michael Ritzert's avatar Michael Ritzert
Browse files

Dump the code used for debugging.

parent 61c5c065
......@@ -67,3 +67,9 @@ set_property PULLDOWN true [get_ports FB_TCK]
set_property PULLUP true [get_ports FB_TDI]
set_property PULLUP true [get_ports FB_TMS]
set_property IOSTANDARD LVCMOS33 [get_ports FB_*]
set_property PACKAGE_PIN AA20 [get_ports {FB_LED[5]}]
set_property PACKAGE_PIN AB21 [get_ports {FB_LED[6]}]
set_property PACKAGE_PIN AA21 [get_ports {FB_LED[7]}]
set_property PACKAGE_PIN Y21 [get_ports {FB_LED[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {FB_LED[*]}]
......@@ -3,7 +3,10 @@ import Readout::pattern_t;
// unit suitable for simulation:
// simple interfaces, no JTAG regs, LVDS receivers, etc.
module T3Controller (
module T3Controller #(
parameter int P_FIFO_WIDTH = 32,
parameter bit [P_FIFO_WIDTH-1:0] P_SYNC_WORD = 32'h01234567
) (
input wire CLK_312,
input wire RESET,
......@@ -12,13 +15,16 @@ module T3Controller (
input wire T3_DATA_OUT,
// control
wire pattern_t PATTERN,
input wire pattern_t PATTERN,
// data
output bit FIFO_WCLK,
input wire FIFO_FREE,
output logic FIFO_WEN,
output bit [31:0] FIFO_WDATA
output bit [P_FIFO_WIDTH-1:0] FIFO_WDATA,
input wire DO_INIT_LINK,
output bit LINK_DETECTED
);
timeunit 1ns; timeprecision 10ps;
......@@ -26,6 +32,9 @@ module T3Controller (
clock_t clock;
bit [ 15:0 ] sent_count;
bit reset_stats;
ClockGen clk_I (
.CLK_312,
.REBOOT(1'b0),
......@@ -42,13 +51,16 @@ module T3Controller (
.RESET(RESET),
.ENABLE(1'b1),
.DO_INIT_LINK(),
.DO_INIT_LINK,
.SEROUT(T3_DATA_OUT),
.WORD_SYNCED(),
.WORD_SYNCED(LINK_DETECTED),
.FIFO_WDATA,
.FIFO_WEN,
.FIFO_FREE
.FIFO_FREE,
.SENT_COUNT( sent_count ),
.RESET_STATS( reset_stats )
);
telegram_sender telegram_I (
......@@ -56,7 +68,10 @@ module T3Controller (
.RESET,
.PATTERN,
.T3_CMD_IN
.T3_CMD_IN,
.SENT_COUNT( sent_count ),
.RESET_STATS( reset_stats )
);
endmodule : T3Controller
......
......@@ -13,6 +13,8 @@ module fpga_top (
input wire FB_TDI,
output bit FB_TDO,
output bit [8:5] FB_LED,
// signals to/from SUS65T3
output bit T3_TMS,
output bit T3_TCK,
......@@ -34,10 +36,11 @@ module fpga_top (
import Readout::*;
// pass through the monitor signal from T3 to an SMA output.
// this can be used to monitor the POR_N operation.
// "Test" pin next to "H5" label
always_comb FB_MONITOR = T3_MON;
always_comb FB_LED[5] = T3_MON;
always_comb FB_LED[6] = 1'b0;
// pass through JTAG from the second FTDI channel to T3
always_comb T3_TMS = FB_TMS;
always_comb T3_TCK = FB_TCK;
......@@ -56,6 +59,8 @@ module fpga_top (
IO_CHANNEL io (.CLK(fifo_wclk));
always_comb io.TX_BYTE_ENABLE = 4'b1111;
bit init_link;
pattern_t pattern;
// I/O pads
......@@ -85,24 +90,37 @@ module fpga_top (
.OB(T3_CMD_IN_N)
);
bit [15:0] usb_write_count;
bit usb_clk_locked;
// other infrastructure
FT245Interface ftdi_I (
.RESET(reset),
.RESET_FTDI(reset),
.RESET(1'b0),
.RESET_FTDI(1'b0),
.FTDI,
.IO(io),
.USB_READ_COUNT (),
.USB_WRITE_COUNT()
.USB_WRITE_COUNT(usb_write_count),
.CLK_LOCKED(usb_clk_locked)
);
always_comb io.RX_READ_ENABLE = 1'b0;
jtag_debug #(
.P_JTAG_CHAIN(4),
.P_LENGTH(18)
) debug4_I (
.DATA({io.TX_FULL, usb_clk_locked, usb_write_count})
);
jtag_reg #(
.P_JTAG_CHAIN(1),
.P_LENGTH(2),
.P_INIT_VALUE(2'b00)
.P_LENGTH(4),
.P_INIT_VALUE(4'b0000)
) jtag1_I (
.VAL({reset, T3_SEQ_RUN}),
.VAL({FB_LED[8], init_link, reset, T3_SEQ_RUN}),
.UPDATED_TOGGLE()
);
......@@ -115,6 +133,17 @@ module fpga_top (
.UPDATED_TOGGLE()
);
/*
bit [19:0] lookback;
always @(negedge clk_312) lookback[19:0] <= {lookback[18:0], t3_data_out};
jtag_reg_read #(
.P_JTAG_CHAIN(3),
.P_LENGTH(21)
) jtag3_I (
.VAL({T3_MON, lookback})
);
*/
always_comb T3_RES_N = !reset;
// logic
......@@ -130,7 +159,9 @@ module fpga_top (
.FIFO_WCLK (fifo_wclk),
.FIFO_FREE (!io.TX_FULL),
.FIFO_WEN (io.TX_WRITE_ENABLE),
.FIFO_WDATA(io.TX_DATA)
.FIFO_WDATA(io.TX_DATA),
.DO_INIT_LINK(init_link)
);
endmodule : fpga_top
`default_nettype wire
......@@ -5,7 +5,9 @@ import readout_8b10b::*;
// build a multi-byte frame from 8b10b words.
module frame_receiver #(
parameter int P_BYTES = 4,
parameter bit P_LEFT_TO_RIGHT = 1'b0
parameter bit P_LEFT_TO_RIGHT = 1'b0,
parameter decoded_8b10b_t P_SYNC_PATTERN = '{ is_k : 1'b1, is_valid : 1'b1, value : cK28_1_value },
parameter bit [ 8*P_BYTES-1:0 ] P_SYNC_WORD = 32'h01234567
) (
input wire WORD_CLK,
input wire WORD_RESET,
......@@ -29,22 +31,29 @@ module frame_receiver #(
.IS_ELAPSED(word_complete)
);
bit sync_received;
always_ff @(posedge WORD_CLK or posedge WORD_RESET) begin : main
if (WORD_RESET) begin
sync_received <= 1'b0;
FRAME_AVAILABLE <= 1'b0;
FRAME_OUT <= {8 * P_BYTES{1'b0}};
active_word <= {8 * P_BYTES{1'b0}};
end else begin
if (ENABLE) begin
sync_received <= (DECODED_IN == P_SYNC_PATTERN);
if (!P_LEFT_TO_RIGHT) begin
active_word <= {active_word[P_BYTES * 8 - 9:0], DECODED_IN.value};
end else begin
active_word <= {DECODED_IN.value, active_word[P_BYTES * 8 - 1:8], DECODED_IN.value};
active_word <= {DECODED_IN.value, active_word[P_BYTES * 8 - 1:8]};
end
FRAME_AVAILABLE <= word_complete;
FRAME_AVAILABLE <= (word_complete || sync_received);
if (word_complete) begin
FRAME_OUT <= active_word;
end else if (sync_received) begin
FRAME_OUT <= P_SYNC_WORD;
end
end
end
......
......@@ -10,7 +10,8 @@ module FT245Interface (
// counts (potentially partial!) words, not bytes
output logic [15:0] USB_READ_COUNT,
output logic [15:0] USB_WRITE_COUNT
output logic [15:0] USB_WRITE_COUNT,
output bit CLK_LOCKED
);
logic logic_reset;
......@@ -18,6 +19,8 @@ module FT245Interface (
FTDI_FIFO intFTDI ();
always_comb CLK_LOCKED = intFTDI.CLK_LOCKED;
// I/O pads, PLL
FTDIIOPads pads_I (
.FTDI(FTDI),
......@@ -48,13 +51,17 @@ module FT245Interface (
IO.RX_ALMOST_EMPTY <= rx_fifo.ALMOST_EMPTY;
end
always_ff @(posedge IO.CLK) begin
if (IO.TX_WRITE_ENABLE) USB_WRITE_COUNT <= USB_WRITE_COUNT + 1'b1;
end
always_ff @(posedge intFTDI.CLK or posedge RESET) begin
if (RESET) begin
USB_WRITE_COUNT <= 16'd0;
//USB_WRITE_COUNT <= 16'd0;
USB_READ_COUNT <= 16'd0;
end else begin
if ((!intFTDI.WR_N) && (!intFTDI.TXE_N)) begin
USB_WRITE_COUNT <= USB_WRITE_COUNT + 1'd1;
//USB_WRITE_COUNT <= USB_WRITE_COUNT + 1'd1;
end
if ((!intFTDI.RD_N) && (!intFTDI.RXF_N)) begin
USB_READ_COUNT <= USB_READ_COUNT + 1'd1;
......
......@@ -29,11 +29,12 @@ module input_framer_bit_skip (
encoded_8b10b_t latched_word;
encoded_8b10b_t latched_word_31;
/*
jtag_debug #(
.P_JTAG_CHAIN(4),
.P_LENGTH(54)
) debug3_I (
.data({
) debug4_I (
.DATA({
// 44
DECODED_IN,
// 43
......@@ -48,6 +49,7 @@ module input_framer_bit_skip (
current_word[0][14:0]
})
);
*/
logic code_err, disp_err;
......
......@@ -3,12 +3,15 @@ module jtag_debug #(
parameter int P_JTAG_CHAIN = 1,
parameter int P_LENGTH = 1
) (
input wire [P_LENGTH-1:0] data
input wire [P_LENGTH-1:0] DATA,
output bit READ
);
timeunit 1ns; timeprecision 10ps;
logic capture, sel, shift, tck, tdi, update, tdo;
always_comb READ = sel && update;
BSCANE2 #(
.JTAG_CHAIN(P_JTAG_CHAIN)
) jtag_I (
......@@ -35,7 +38,7 @@ module jtag_debug #(
.STATE_SHIFT_DR(shift),
.STATE_UPDATE_DR(update),
.TDO(tdo),
.VAL(data)
.VAL(DATA)
);
endmodule : jtag_debug
`timescale 1ns/1ps
`default_nettype none
module jtag_reg_read #(
parameter int P_JTAG_CHAIN = 0,
parameter int P_LENGTH = 1
) (
input wire [ P_LENGTH-1:0 ] VAL
);
logic capture, sel, shift, tck, tdi, update, tdo;
BSCANE2 #(
.JTAG_CHAIN( P_JTAG_CHAIN )
) jtag_I(
.CAPTURE( capture ),
.DRCK(),
.RESET(),
.RUNTEST(),
.SEL( sel ),
.SHIFT( shift ),
.TCK( tck ),
.TDI( tdi ),
.TMS(),
.UPDATE( update ),
.TDO( tdo )
);
jtag_user_reg_read #(
.P_LENGTH( P_LENGTH )
) reg_I(
.TCK( tck ),
.TDI( tdi ),
.SELECT( sel ),
.STATE_CAPTURE_DR( capture ),
.STATE_SHIFT_DR( shift ),
.STATE_UPDATE_DR( update ),
.TDO( tdo ),
.VAL( VAL )
);
endmodule : jtag_reg_read
`default_nettype wire
\ No newline at end of file
......@@ -9,7 +9,9 @@ module push_data_provider (
input wire ENABLE,
input wire pattern_t DATA_IN,
output pattern_word_t DATA_OUT
output pattern_word_t DATA_OUT,
output bit [ 15:0 ] SENT_COUNT,
input wire RESET_STATS
);
timeunit 1ns; timeprecision 10ps;
......@@ -18,8 +20,13 @@ module push_data_provider (
bit [5:0] current_word;
always_ff @(posedge WORD_CLK) begin
if (current_word >= DATA_IN.pattern_length - 1) current_word <= 6'd0;
if (current_word >= DATA_IN.pattern_length - 1) begin
current_word <= 6'd0;
if (!RESET_STATS) SENT_COUNT <= SENT_COUNT + 1'd1;
end
else current_word <= current_word + 6'd1;
if (RESET_STATS) SENT_COUNT <= 16'd0;
end
always_comb DATA_OUT <= ENABLE ? DATA_IN.data[current_word] : cIDLE_WORD;
......
......@@ -3,7 +3,10 @@
import Readout::*;
import readout_8b10b::*;
module push_receiver (
module push_receiver #(
parameter int P_FIFO_WIDTH = 32,
parameter bit [P_FIFO_WIDTH-1:0] P_SYNC_WORD = 32'h01234567
) (
input clock_t CLOCK,
input wire RESET,
......@@ -12,17 +15,19 @@ module push_receiver (
input wire SEROUT,
output logic WORD_SYNCED,
output bit [31:0] FIFO_WDATA,
output bit [P_FIFO_WIDTH-1:0] FIFO_WDATA,
output logic FIFO_WEN,
input wire FIFO_FREE
input wire FIFO_FREE,
// debug only
input wire [ 15:0 ] SENT_COUNT,
output bit RESET_STATS
);
timeunit 1ns; timeprecision 10ps;
decoded_8b10b_t decoded_in;
bit [31:0] frame;
logic frame_available;
logic [1:0] frame_available_sync;
reg [7:0] hit_count = 8'd0;
logic [2:0] bit_phase;
logic shift_words;
......@@ -50,7 +55,7 @@ module push_receiver (
.UPLINK_SERIN(SEROUT),
.BIT_PHASE(bit_phase),
.SHIFT_WORDS(shift_words),
.SELECT_EDGE(1'b1),
.SELECT_EDGE(1'b0), // changed!
.DECODED_IN(decoded_in),
......@@ -64,23 +69,62 @@ module push_receiver (
.WORD_CLK(CLOCK.CLK_31),
.WORD_RESET(RESET),
.ENABLE(ENABLE && !DO_INIT_LINK),
.FRAME_OUT(frame),
.FRAME_OUT(FIFO_WDATA),
.FRAME_AVAILABLE(frame_available),
.DECODED_IN(decoded_in)
);
always_comb FIFO_WDATA = frame;
always_ff @(posedge CLOCK.CLK_62) begin
frame_available_sync[1:0] <= {frame_available_sync[0], frame_available};
FIFO_WEN <= (frame_available_sync == 2'b01) && FIFO_FREE;
always_ff @(posedge CLOCK.CLK_31) begin
FIFO_WEN <= frame_available && FIFO_FREE;
end
always @(posedge CLOCK.CLK_62) begin
if (frame_available_sync == 2'b01) begin
always @(posedge CLOCK.CLK_31) begin
if (frame_available) begin
hit_count <= hit_count + 1'd1;
end
end
// debug
bit [15:0] frame_count;
decoded_8b10b_t [35:0] history_updating;
decoded_8b10b_t [35:0] history_frozen;
bit [7:0] inv_count;
bit reset_stats_tck;
bit [1:0] reset_stats_sync;
jtag_debug #(
.P_JTAG_CHAIN(3),
.P_LENGTH(36*10+8+16+16)
) debug3_I (
.DATA({
SENT_COUNT,
inv_count,
frame_count,
history_frozen
}),
.READ(reset_stats_tck)
);
always_ff @(posedge CLOCK.CLK_31) begin
history_updating[35:0] <= { history_updating[34:0], decoded_in };
reset_stats_sync[1:0] <= {reset_stats_sync[0], reset_stats_tck};
RESET_STATS <= reset_stats_sync[1:0] == 2'b01;
if (decoded_in.is_k && decoded_in.value == 8'h3C ) begin
history_frozen <= history_updating;
if (!RESET_STATS) frame_count <= frame_count + 1'd1;
end
if (!decoded_in.is_valid) begin
if (!RESET_STATS) inv_count <= inv_count + 1'd1;
end
if (RESET_STATS) begin
frame_count <= 16'd0;
inv_count <= 8'd0;
end
end
endmodule : push_receiver
`default_nettype wire
......@@ -6,8 +6,10 @@ import Readout::pattern_t;
module telegram_sender (
input clock_t CLOCK,
input wire RESET,
input pattern_t PATTERN,
output bit T3_CMD_IN
input wire pattern_t PATTERN,
output bit T3_CMD_IN,
output bit [ 15:0 ] SENT_COUNT,
input wire RESET_STATS
);
timeunit 1ns; timeprecision 10ps;
......@@ -20,7 +22,9 @@ module telegram_sender (
.WORD_RESET(RESET),
.ENABLE(1'b1),
.DATA_IN(PATTERN),
.DATA_OUT(ser_word)
.DATA_OUT(ser_word),
.SENT_COUNT,
.RESET_STATS
);
// command telegram to ASIC
......@@ -34,4 +38,29 @@ module telegram_sender (
.SEROUT(T3_CMD_IN),
.BYTE_IN(ser_word)
);
/*
bit [369:0] live;
bit [369:0] sampled;
bit [9:0] trigger_win;
always_comb trigger_win <= live[369-:10];
const bit [9:0] K28_1_serial = 10'b1001111100;
always @(posedge CLOCK.CLK_312)
begin
live[369:0] <= {live[368:0], T3_CMD_IN};
if ((trigger_win == K28_1_serial) || (trigger_win == ~K28_1_serial)) begin
sampled <= live;
end
end
jtag_debug #(
.P_JTAG_CHAIN(4),
.P_LENGTH(370)
) debug4_I (
.DATA(sampled)
);
*/
endmodule : telegram_sender
......@@ -26,9 +26,6 @@ module testbench ();
.CLK_312(clk_312),
.RESET (RESET),
.T3_RES_N(),
.T3_SEQ_RUN,
.T3_CMD_IN,
.T3_DATA_OUT,
......@@ -81,18 +78,22 @@ module testbench ();
);
subframe_cmd_t command = '{
ro_enable : 2'b01,
ro_enable : 2'b11,
RAM_address : 8'h00,
RAM_address_is_relative : 1'b0,
word_sel : WORD_LOW,
f : F_STORE
word_sel : WORD_FULL,
f : F_INCREMENT
};
initial begin
@(posedge T3_POR_N);
@(negedge clk_312);
// en_pixel_control
force ASIC_I.user_reg_global_reg_I.VAL[80] = 1'b1;
// conversion.LSB_correction
force ASIC_I.user_reg_global_reg_I.VAL[86] = 1'b1;
T3_RES_N = 1'b0;
T3_SEQ_RUN = 1'b0;
@(negedge clk_312);
@(negedge clk_312);
T3_RES_N = 1'b1;
......@@ -117,7 +118,7 @@ module testbench ();
pattern.data[4] = cSYNC_WORD;
pattern.data[5] = '{is_k : 1'b0, value : command[15:8]};
pattern.data[6] = '{is_k : 1'b0, value : command[7:0]};
pattern.data[7] = '{is_k : 1'b0, value : 8'h00};
pattern.data[7] = '{is_k : 1'b0, value : 8'H00};