Commit 37c0aaaf authored by David Schimansky's avatar David Schimansky
Browse files

In firmware:

- Add input for rf clock and trigger
- Add triggered RUN that turns on Sequencer only for one subframe after external trigger has been detected
- Add on-FPGA jtag control register for enable/disable of triggered readout


In software:
- Add corresponding jtag register bit in dyn cntrl jtag register data structure
- Add checkbox in Telegram gui to control triggered readout
parent e8548257
......@@ -19,6 +19,16 @@ set_property PACKAGE_PIN J17 [get_ports ASIC_DATA_OUT_N]
set_property PACKAGE_PIN J19 [get_ports CLK_312_P]
set_property PACKAGE_PIN H19 [get_ports CLK_312_N]
set_property PACKAGE_PIN L3 [get_ports EXT_CLK_352_P]
set_property PACKAGE_PIN K3 [get_ports EXT_CLK_352_N]
set_property PACKAGE_PIN K1 [get_ports EXT_TRIG_P]
set_property PACKAGE_PIN J1 [get_ports EXT_TRIG_N]
set_property PACKAGE_PIN K2 [get_ports ASIC_SEQ_RUN]
#GPIO0
set_property PACKAGE_PIN U17 [get_ports ASIC_SEQ_RUN_MON]
......@@ -27,7 +37,8 @@ set_property PACKAGE_PIN W17 [get_ports IO_FIFO_WRITE_EN]
#GPIO3
set_property PACKAGE_PIN V17 [get_ports INIT_LINK_MON]
#GPIO4
set_property PACKAGE_PIN AB18 [get_ports LINK_DETECTED_MON]
#set_property PACKAGE_PIN AB18 [get_ports LINK_DETECTED_MON]
set_property PACKAGE_PIN AB18 [get_ports EXT_CLK_352_MON]
......@@ -105,6 +116,18 @@ set_property IOSTANDARD LVDS_25 [get_ports ASIC_DATA_OUT_N]
set_property IOSTANDARD LVDS_25 [get_ports CLK_312_P]
set_property IOSTANDARD LVDS_25 [get_ports CLK_312_N]
#set_property IOSTANDARD LVCMOS12 [get_ports EXT_CLK_352_P]
#set_property IOSTANDARD LVCMOS12 [get_ports EXT_CLK_352_N]
set_property IOSTANDARD LVDS_25 [get_ports EXT_CLK_352_P]
set_property IOSTANDARD LVDS_25 [get_ports EXT_CLK_352_N]
set_property IOSTANDARD LVDS_25 [get_ports EXT_TRIG_P]
set_property IOSTANDARD LVDS_25 [get_ports EXT_TRIG_N]
set_property IOSTANDARD LVCMOS18 [get_ports EXT_CLK_352_MON]
set_property IOSTANDARD LVCMOS12 [get_ports ASIC_SEQ_RUN]
set_property IOSTANDARD LVCMOS18 [get_ports ASIC_SEQ_RUN_MON]
......@@ -112,7 +135,7 @@ set_property IOSTANDARD LVCMOS18 [get_ports IO_FIFO_WRITE_EN]
set_property IOSTANDARD LVCMOS18 [get_ports INIT_LINK_MON]
set_property IOSTANDARD LVCMOS18 [get_ports LINK_DETECTED_MON]
#set_property IOSTANDARD LVCMOS18 [get_ports LINK_DETECTED_MON]
......
......@@ -18,6 +18,9 @@ module ASIC_Controller #(
// control
input wire pattern_t PATTERN,
input wire TRIGGER_FROM_SYNCHROTRON,
input wire TRIGGERED_READOUT,
// data
output bit FIFO_WCLK,
......@@ -53,6 +56,24 @@ module ASIC_Controller #(
wire subframe_start;
wire subframe_start_delayed;
//wire [7:0] subframe_length_in_10b_words;
//assign subframe_length_in_10b_words = PATTERN.pattern_length;
reg trigger_run = 1'b0;
always @(posedge clock.CLK_312) begin
if(TRIGGER_FROM_SYNCHROTRON) begin
trigger_run <= 1'b1;
end else begin
if(ASIC_SEQ_RUN_SYNC) begin
trigger_run <= 1'b0;
end else begin
trigger_run <= trigger_run;
end
end
end
wire asic_seq_run_int;
assign asic_seq_run_int = TRIGGERED_READOUT ? trigger_run : ASIC_SEQ_RUN_ASYNC;
// always @(posedge clock.CLK_31) begin
// subframe_start_del <= {subframe_start, subframe_start_del[40:1]};
......@@ -73,6 +94,8 @@ module ASIC_Controller #(
bit [P_FIFO_WIDTH-1:0] FIFO_WDATA_int;
assign FIFO_WDATA = FIFO_WDATA_int + {BYTES_PER_FIFO_WORD{8'h01}}; // Add 1 to every byte that is written to FTDI FIFO to avoid zero suppression
always @(posedge clock.CLK_62) begin
if(clock.CLK_31 && subframe_start_delayed) begin
ASIC_SEQ_RUN_SYNC <= ASIC_SEQ_RUN_ASYNC;
......@@ -82,6 +105,7 @@ module ASIC_Controller #(
end
//always_comb FIFO_WCLK = clock.CLK_31;
assign FIFO_WCLK = clock.CLK_31;
......
......@@ -3,6 +3,11 @@ import Readout::*;
module XIDer_top (
input wire CLK_312_P,
input wire CLK_312_N,
input wire EXT_CLK_352_P,
input wire EXT_CLK_352_N,
input wire EXT_TRIG_P,
input wire EXT_TRIG_N,
// BYPASS OF ASIC JTAG SIGNALS FROM FTDI TO ASIC
input wire JTAG_PETA_CLK_FTDI,
......@@ -31,7 +36,8 @@ module XIDer_top (
output wire IO_FIFO_WRITE_EN,
output wire INIT_LINK_MON,
output wire LINK_DETECTED_MON
//output wire LINK_DETECTED_MON
output wire EXT_CLK_352_MON
);
......@@ -54,10 +60,13 @@ module XIDer_top (
wire reset;
wire daq_reset;
wire [6:0] subframe_start_delay;
wire triggered_readout;
wire trigger_from_synchrotron;
logic long_frames;
pattern_t pattern;
wire clk_312;
wire ext_clk_352;
wire fifo_wclk;
IO_CHANNEL io (.CLK(fifo_wclk));
......@@ -69,13 +78,14 @@ module XIDer_top (
assign JTAG_TMS_ASIC = JTAG_PETA_TMS_FTDI;
assign ASIC_RESET_N = !reset;
// assign EXT_CLK_P_MON = EXT_CLK_P;
jtag_reg #(
.P_JTAG_CHAIN(1),
.P_LENGTH(12),
.P_INIT_VALUE(12'd0)
.P_LENGTH(13),
.P_INIT_VALUE(13'd0)
) jtag1_I (
.VAL({subframe_start_delay, daq_reset, long_frames, init_link, reset, asic_seq_run}),
.VAL({triggered_readout, subframe_start_delay, daq_reset, long_frames, init_link, reset, asic_seq_run}),
.UPDATED_TOGGLE()
);
jtag_reg #(
......@@ -105,6 +115,8 @@ module XIDer_top (
.ASIC_SEQ_RUN_SYNC(ASIC_SEQ_RUN),
.PATTERN(pattern),
.TRIGGER_FROM_SYNCHROTRON(trigger_from_synchrotron),
.TRIGGERED_READOUT(triggered_readout),
.FIFO_WCLK(fifo_wclk),
.FIFO_ALMOST_FULL(io.TX_ALMOST_FULL),
......@@ -167,6 +179,16 @@ module XIDer_top (
.O (clk_312)
);
IBUFDS #(
.IOSTANDARD("LVDS_25"),
.DIFF_TERM ("FALSE")
) ibufExtTrig_I (
.I (EXT_TRIG_P),
.IB(EXT_TRIG_N),
.O (trigger_from_synchrotron)
);
OBUF #(
.IOSTANDARD("LVCMOS18")
) ibufAsicRun_I (
......@@ -188,10 +210,36 @@ module XIDer_top (
.O(INIT_LINK_MON)
);
IBUFDS #(
.IOSTANDARD("LVDS_25"),
.DIFF_TERM ("FALSE")
) ibufExtClk_I (
.I (EXT_CLK_352_P),
.IB(EXT_CLK_352_N),
.O (ext_clk_352)
);
reg ext_clk_352_mon = 1'b0;
reg [8:0] clk_cnt = 9'd0;
always @(posedge ext_clk_352) begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 9'd100) begin
clk_cnt <= 9'd0;
ext_clk_352_mon <= !ext_clk_352_mon;
end
end
// OBUF #(
// .IOSTANDARD("LVCMOS18")
// ) obuflinkdetected_I (
// .I(link_detected),
// .O(LINK_DETECTED_MON)
// );
OBUF #(
.IOSTANDARD("LVCMOS18")
) obuflinkdetected_I (
.I(link_detected),
.O(LINK_DETECTED_MON)
) obufextclk_I (
.I(ext_clk_352_mon),
.O(EXT_CLK_352_MON)
);
endmodule
......@@ -248,7 +248,7 @@ class dyn():
def __init__(self, urJTAG_FPGAChain, FPGA_found, cmdWriter):
self.log = log.getLogger("DynCntrl")
self.urc_FPGA = urJTAG_FPGAChain
self.jtag_dyn_len = 12
self.jtag_dyn_len = 13
self.jtag_dyn = JTAG_reg.JTAG_reg("init_res_run", address=2, size=self.jtag_dyn_len, content=0)
# self.urc_FPGA.add_register(self.jtag_dyn.get_name(), self.jtag_dyn.get_size())
......@@ -352,7 +352,7 @@ class dyn():
content_str = list(format(content, '0{}b'.format(self.jtag_dyn_len)))
delay_str = list(format(delay, '07b'))
content_str[0:7] = delay_str
content_str[1:8] = delay_str
# content_str[0:7] = delay_str[::-1]
new_content_str = ''.join(content_str)
new_content = int(new_content_str, 2)
......@@ -398,6 +398,18 @@ class dyn():
self.jtag_telegram.set_content(telegram + telegramLength)
self.myCmdWriter.writeCmds(np.array([self.jtag_telegram]), self.urc_FPGA)
def set_triggered_readout(self, triggered_ro):
content = self.jtag_dyn.get_content()
content_str = list(format(content, '0{}b'.format(self.jtag_dyn_len)))
content_str[0] = str(int(triggered_ro))
# content_str[0:7] = delay_str[::-1]
new_content_str = ''.join(content_str)
new_content = int(new_content_str, 2)
self.jtag_dyn.set_content(new_content)
self.myCmdWriter.writeCmds(np.array([self.jtag_dyn]), self.urc_FPGA)
def sync_idle_pattern(self, fillLength=46):
# self.myTelegram.set_head(self.kWords["SYNC"])
......
......@@ -1713,6 +1713,7 @@ class QXTelegram(qtw.QWidget):
self.createLayout()
self.initFromFile()
self.en = 0
self.trig_ro = False
#self.fill = 46
self.update()
......@@ -1738,9 +1739,20 @@ class QXTelegram(qtw.QWidget):
checkBox_state.stateChanged.connect(self.enable_cmd)
hlayout_state.addWidget(label_state, alignment=qtc.Qt.AlignRight)
hlayout_state.addWidget(checkBox_state, alignment=qtc.Qt.AlignLeft)
# hlayout_tot.addLayout(hlayout_empty)
# hlayout_tot.addLayout(hlayout_state)
label_trigger_ro = qtw.QLabel("Triggered Readout")
triggeredReadout_cb = qtw.QCheckBox()
hlayout_state.addWidget(label_trigger_ro, alignment=qtc.Qt.AlignRight)
hlayout_state.addWidget(triggeredReadout_cb, alignment=qtc.Qt.AlignLeft)
hlayout_tot.addLayout(hlayout_empty)
hlayout_tot.addLayout(hlayout_state)
vlayout.addLayout(hlayout_tot)
......@@ -1894,7 +1906,7 @@ class QXTelegram(qtw.QWidget):
vlayout.addWidget(adjustBox_rd)
vlayout.addWidget(progBtn)
self.buttonsAndBoxes = np.array([telegramFills_spBox, comboBox_head, self.spinBox_RAMwrAdd, checkBox, comboBox2, comboBox, spinBox_rd, comboBox_ro_bytes])
self.buttonsAndBoxes = np.array([telegramFills_spBox, comboBox_head, self.spinBox_RAMwrAdd, checkBox, comboBox2, comboBox, spinBox_rd, comboBox_ro_bytes, triggeredReadout_cb])
self.enableButtonsAndBoxes(False)
# for button in self.buttonsAndBoxes:
......@@ -1902,6 +1914,9 @@ class QXTelegram(qtw.QWidget):
# self.loadTelConfBtn.setEnabled(False)
# self.saveTelConfBtn.setEnabled(False)
def toggle_triggered_readout(self, trig_ro):
self.trig_ro = not self.trig_ro
self.jtag.myASICDynCntrl.set_triggered_readout(trig_ro) #TODO: Get rid of duplicated command storage in GUI and dynCntrl class
def setConfigPathLabel(self, path):
......
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