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1539ea17
·
Merge branch 'SUS65T3-final'
·
Dec 01, 2021
move-to-peta-pyGUI
f74effd0
·
In software:
·
Nov 29, 2021
move-to-peta
7859cf22
·
Update vivado project
·
Nov 18, 2021
move-to-peta-repltest
c6999a5b
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Check functionality with python repl from DMAK setup with ASICConf class as example.
·
Nov 18, 2021
SUS65T4-DMAKDAQ
a6c71611
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Update Vivado project
·
Nov 03, 2021
SUS65T5-digital-2
357ce195
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Simulate one readout cycle.
·
Sep 20, 2021
SUS65T5-digital
30ba14f9
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Automatically reset the entire digital part during POR.
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Aug 27, 2021
feature/ddyn-ClkCPFine
e8d88603
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Add extra sequencer track (ddyn12) for charge pump of fine stage
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Jul 29, 2021
include-RAM
82d89195
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Add M8 blockage near the FE's MIMCAPs.
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Jul 21, 2021
feature/partitions
83b80068
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Add scripts for the partitioned flow (2 versions).
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Jul 16, 2021
feature/ddr-ddyn
cf1e3f1b
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Output the SDF last.
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Jun 10, 2021
feature/genus-jtag
77c4a978
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Import the new SV IC RESET register.
·
May 25, 2021
feature/pads
7be7eeee
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Work towards placing the digital I/O pads in the digital flow.
·
May 25, 2021
feature/jtag-core
54f1c3fc
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Move the DAC register to jtag_top.
·
Apr 04, 2021
test/simple-logic
e2807b3d
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Simplify checking the state.
·
Mar 29, 2021
feature/seq-negedge
db9ab84c
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Put option to output sequencer tracks on falling edge into DDYN_OutReg instead of Track itself
·
Mar 22, 2021
feature/remove-hold
593d4a9c
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Remove the hold configuration register.
·
Mar 16, 2021
SUS65T3-final
72188aa2
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Merge branch 'sus_dev'
·
Mar 11, 2021
SUS65T3-digital
6a279bea
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Fixes for linter warnings.
·
Feb 09, 2021
sus_dev_pygui
7c44c6fb
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add "new config" button to register and sequencer
·
Feb 01, 2021
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