ct2: reorganize tests

parent c797f2c8
......@@ -5,6 +5,14 @@
# Copyright (c) 2016 Beamline Control Unit, ESRF
# Distributed under the GNU LGPLv3. See LICENSE for more info.
"""
Required hardware: P201 card installed in lid00c
Required software: Running bliss-ct2-server on tcp::/lid00c:8909
To change PC replace in `../test-configuration/ct2.yml` the address
of the P201 card
"""
import time
import contextlib
......@@ -20,10 +28,11 @@ from bliss.controllers.ct2.device import AcqMode, AcqStatus, StatusSignal
TEN_KHz = 10000
ERROR_MARGIN = 10E-3 # 10ms
class EventReceiver(object):
"""Context manager which accumulates data"""
def __init__(self, device):
self.device = device
self.finish = Event()
......@@ -46,13 +55,20 @@ class EventReceiver(object):
dispatcher.disconnect(self, sender=self.device)
@pytest.fixture(params=[1, 5], ids=['1 point', '5 points'])
@pytest.fixture(params=[1, 10, 100], ids=['1 point', '10 points', '100 points'])
def device(request, beacon):
#beacon.reload()
"""
Requirements to run this fixture:
hardware: P201 card installed in lid00c
software: Running bliss-ct2-server on tcp::/lid00c:8909
"""
beacon.reload()
device = beacon.get('p201')
device.timer_freq = 1E8
device.timer_freq = 12.5E6
device.acq_nb_points = request.param
return device
yield device
device.close()
def data_tests(device, expected_data):
......@@ -79,10 +95,11 @@ def data_tests(device, expected_data):
def soft_trigger_points(device, n, period):
while n > 0:
sleep(period)
i, start = 0, time.time()
while i < n:
sleep((start + (i+1)*period) - time.time())
device.trigger_point()
n -= 1
i += 1
def test_internal_trigger_single_wrong_config(device):
......@@ -105,11 +122,13 @@ def test_internal_trigger_single(device):
Required hardware: P201 card installed in lid00c
Required software: Running bliss-ct2-server on tcp::/lid00c:8909
"""
expo_time = 0.02
point_period = expo_time + 0.01
freq = device.timer_freq
nb_points = device.acq_nb_points
device.acq_mode = AcqMode.IntTrigSingle
device.acq_expo_time = expo_time = 0.09
device.acq_point_period = point_period = 0.11
device.acq_expo_time = expo_time
device.acq_point_period = point_period
device.acq_channels = 3,
with EventReceiver(device) as receiver:
......@@ -117,10 +136,9 @@ def test_internal_trigger_single(device):
device.start_acq()
receiver.finish.wait()
# allow 10ms for communication
elapsed = receiver.end - receiver.start
expected_elapsed = nb_points * point_period
assert elapsed == pytest.approx(expected_elapsed, abs=1e-2)
assert elapsed == pytest.approx(expected_elapsed, abs=ERROR_MARGIN)
timer_ticks = int(freq * expo_time)
ch_3_value = int(TEN_KHz * expo_time)
......@@ -129,6 +147,34 @@ def test_internal_trigger_single(device):
data_tests(device, expected_data)
def test_internal_trigger_single_stop_acq(device):
"""
Required hardware: P201 card installed in lid00c
Required software: Running bliss-ct2-server on tcp::/lid00c:8909
"""
expo_time = 0.02
point_period = expo_time + 0.01
freq = device.timer_freq
nb_points = device.acq_nb_points
device.acq_mode = AcqMode.IntTrigSingle
device.acq_expo_time = expo_time
device.acq_point_period = point_period
device.acq_channels = 3,
expected_elapsed = nb_points * point_period
with EventReceiver(device) as receiver:
device.prepare_acq()
device.start_acq()
# stop around 10%
sleep(0.1 * expected_elapsed)
device.stop_acq()
start_stop = time.time()
receiver.finish.wait()
end_stop = time.time()
assert (end_stop - start_stop) < 10E-3 # allow 10ms for stop
def test_internal_trigger_multi_wrong_config(device):
"""
Required hardware: P201 card installed in lid00c
......@@ -149,15 +195,16 @@ def test_internal_trigger_multi(device):
Required hardware: Only P201 card is required
Required software: Running bliss-ct2-server on tcp::/lid00c:8909
"""
soft_point_period = 0.2
expo_time = 0.02
soft_point_period = expo_time + 0.01
freq = device.timer_freq
nb_points = device.acq_nb_points
device.acq_mode = AcqMode.IntTrigMulti
device.acq_expo_time = expo_time = 0.09
device.acq_expo_time = expo_time
device.acq_point_period = None
device.acq_channels = 3,
nb_triggers = nb_points - 1
with EventReceiver(device) as receiver:
device.prepare_acq()
device.start_acq()
......@@ -168,10 +215,9 @@ def test_internal_trigger_multi(device):
assert trigger_task.ready()
assert trigger_task.exception == None
# allow 10ms for communication
elapsed = receiver.end - receiver.start
expected_elapsed = (nb_points - 1) * soft_point_period + 1 * expo_time
assert elapsed == pytest.approx(expected_elapsed, abs=1e-2)
assert elapsed == pytest.approx(expected_elapsed, abs=ERROR_MARGIN)
timer_ticks = int(freq * expo_time)
ch_3_value = int(TEN_KHz * expo_time)
......@@ -193,24 +239,18 @@ def test_software_trigger_readout_wrong_config(device):
with pytest.raises(zerorpc.RemoteError):
device.prepare_acq()
# device.acq_expo_time = 1.1
# device.acq_point_period = None
#
# # Should not be able to prepare soft trigger readout with expo time
# with pytest.raises(zerorpc.RemoteError):
# device.prepare_acq()
def test_software_trigger_readout(device):
expo_time = None
soft_point_period = 0.11
freq = device.timer_freq
nb_points = device.acq_nb_points
device.acq_mode = AcqMode.SoftTrigReadout
device.acq_expo_time = expo_time = None
device.acq_expo_time = expo_time
device.acq_point_period = None
device.acq_channels = 3,
nb_triggers = nb_points
with EventReceiver(device) as receiver:
device.prepare_acq()
device.start_acq()
......@@ -221,14 +261,12 @@ def test_software_trigger_readout(device):
assert trigger_task.ready()
assert trigger_task.exception == None
# allow 10ms for communication
elapsed = receiver.end - receiver.start
expected_elapsed = nb_points * soft_point_period
assert elapsed == pytest.approx(expected_elapsed, abs=1e-2)
assert elapsed == pytest.approx(expected_elapsed, abs=ERROR_MARGIN)
timer_ticks = int(freq * soft_point_period)
ch_3_value = int(TEN_KHz * soft_point_period)
expected_data = numpy.array([(ch_3_value, timer_ticks, i)
for i in range(nb_points)])
data_tests(device, expected_data)
......@@ -10,59 +10,6 @@ import unittest
from bliss.controllers.ct2 import card
class TestCtConfig(unittest.TestCase):
def test_ctconfig_empty(self):
cfg = card.CtConfig()
self.assertEqual(card.CtConfig.toint(cfg), 0)
def test_ctconfig_init_with_1_param(self):
clock_1_mhz = 0x03
self.assertEqual(clock_1_mhz, card.CtClockSrc.CLK_1_MHz.value)
cfg = card.CtConfig(clock_source=card.CtClockSrc.CLK_1_MHz)
self.assertEqual(cfg.value, card.CtClockSrc.CLK_1_MHz.value)
self.assertEqual(cfg.clock_source, card.CtClockSrc.CLK_1_MHz)
def test_ctconfig_init_with_params(self):
reg = 0x04 | (0x1E << 7) | (0x09 << 13) | (0x52 << 20) | (1 << 30) | (0 << 31)
cfg = card.CtConfig(clock_source=card.CtClockSrc.CLK_12_5_MHz,
gate_source=card.CtGateSrc.CT_6_GATE_ENVELOP,
hard_start_source=card.CtHardStartSrc.CH_9_RISING_EDGE,
hard_stop_source=card.CtHardStopSrc.CT_10_EQ_CMP_10,
reset_from_hard_soft_stop=True,
stop_from_hard_stop=False)
self.assertEqual(card.CtConfig.toint(cfg), reg)
self.assertEqual(cfg['clock_source'], card.CtClockSrc.CLK_12_5_MHz)
self.assertEqual(cfg['gate_source'], card.CtGateSrc.CT_6_GATE_ENVELOP)
self.assertEqual(cfg['hard_start_source'], card.CtHardStartSrc.CH_9_RISING_EDGE)
self.assertEqual(cfg['hard_stop_source'], card.CtHardStopSrc.CT_10_EQ_CMP_10)
self.assertTrue(cfg['reset_from_hard_soft_stop'])
self.assertFalse(cfg['stop_from_hard_stop'])
def test_ctconfig_set(self):
cfg = card.CtConfig()
self.assertEqual(cfg.value, 0)
cfg['clock_source'] = card.CtClockSrc.CLK_10_KHz
reg = 0x1
self.assertEqual(cfg['clock_source'], card.CtClockSrc.CLK_10_KHz)
self.assertEqual(cfg.value, card.CtClockSrc.CLK_10_KHz.value)
self.assertEqual(cfg.value, reg)
cfg['hard_start_source'] = card.CtHardStartSrc.CT_6_START_STOP
reg = 0x1 | (0x42 << 13)
self.assertEqual(cfg.clock_source, card.CtClockSrc.CLK_10_KHz)
self.assertEqual(cfg['clock_source'], card.CtClockSrc.CLK_10_KHz)
self.assertEqual(cfg.hard_start_source, card.CtHardStartSrc.CT_6_START_STOP)
self.assertEqual(cfg['hard_start_source'], card.CtHardStartSrc.CT_6_START_STOP)
self.assertEqual(cfg.value, reg)
class TestP201(unittest.TestCase):
def setUp(self):
......
# -*- coding: utf-8 -*-
#
# This file is part of the bliss project
#
# Copyright (c) 2016 Beamline Control Unit, ESRF
# Distributed under the GNU LGPLv3. See LICENSE for more info.
"""
CT2 pure software tests (no hardware required)
"""
from bliss.controllers.ct2.card import CtConfig, CtClockSrc, CtGateSrc
from bliss.controllers.ct2.card import CtHardStartSrc, CtHardStopSrc
def test_ctconfig_empty():
cfg = CtConfig()
assert CtConfig.toint(cfg) == 0
def test_ctconfig_init_with_1_param():
clock_1_mhz = 0x03
assert clock_1_mhz == CtClockSrc.CLK_1_MHz.value
cfg = CtConfig(clock_source=CtClockSrc.CLK_1_MHz)
assert CtConfig.toint(cfg) == CtClockSrc.CLK_1_MHz.value
assert cfg['clock_source'] == CtClockSrc.CLK_1_MHz
def test_ctconfig_init_with_params():
reg = 0x04 | (0x1E << 7) | (0x09 << 13) | (0x52 << 20) | (1 << 30) | (0 << 31)
cfg = CtConfig(clock_source=CtClockSrc.CLK_12_5_MHz,
gate_source=CtGateSrc.CT_6_GATE_ENVELOP,
hard_start_source=CtHardStartSrc.CH_9_RISING_EDGE,
hard_stop_source=CtHardStopSrc.CT_10_EQ_CMP_10,
reset_from_hard_soft_stop=True,
stop_from_hard_stop=False)
assert CtConfig.toint(cfg) == reg
assert cfg['clock_source'] == CtClockSrc.CLK_12_5_MHz
assert cfg['gate_source'] == CtGateSrc.CT_6_GATE_ENVELOP
assert cfg['hard_start_source'] == CtHardStartSrc.CH_9_RISING_EDGE
assert cfg['hard_stop_source'] == CtHardStopSrc.CT_10_EQ_CMP_10
assert cfg['reset_from_hard_soft_stop']
assert not cfg['stop_from_hard_stop']
def test_ctconfig_set():
cfg = CtConfig()
cfg['clock_source'] = CtClockSrc.CLK_10_KHz
reg = 0x1
assert cfg['clock_source'] == CtClockSrc.CLK_10_KHz
assert CtConfig.toint(cfg) == CtClockSrc.CLK_10_KHz.value
assert CtConfig.toint(cfg) == reg
cfg['hard_start_source'] = CtHardStartSrc.CT_6_START_STOP
reg = 0x1 | (0x42 << 13)
assert cfg['clock_source'] == CtClockSrc.CLK_10_KHz
assert cfg['hard_start_source'] == CtHardStartSrc.CT_6_START_STOP
assert CtConfig.toint(cfg) == reg
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment