Implement cmd_dma, input_filter, interrupts

parent fc8be33d
This diff is collapsed.
"""
Simple example counting until a certain value on a counter
"""
......@@ -18,7 +17,7 @@ except:
sys.path.append(this_dir)
from bliss.controllers import ct2
from bliss.controllers.ct2 import P201, Clock, LevelOut, CtConfig, OutputSrc
from bliss.controllers.ct2 import P201, Clock, Level, CtConfig, OutputSrc
from bliss.controllers.ct2 import CtClockSrc, CtGateSrc, CtHardStartSrc, CtHardStopSrc
......@@ -44,11 +43,11 @@ def main():
p201.reset()
p201.software_reset()
# internal clock 40 Mhz
p201.set_clock(Clock.CLK_40_MHz)
# internal clock 100 Mhz
p201.set_clock(Clock.CLK_100_MHz)
# channel 10 output: counter 10 gate envelop
p201.set_level_out({counter: LevelOut(TTL=True)})
p201.set_output_level({counter: Level.TTL})
# no 50 ohm adapter
p201.set_50ohm_adapters({})
......
......@@ -18,7 +18,7 @@ except:
sys.path.append(this_dir)
from bliss.controllers import ct2
from bliss.controllers.ct2 import P201, Clock, LevelOut, CtConfig, OutputSrc
from bliss.controllers.ct2 import P201, Clock, Level, CtConfig, OutputSrc
from bliss.controllers.ct2 import CtClockSrc, CtGateSrc, CtHardStartSrc, CtHardStopSrc
......@@ -41,11 +41,11 @@ def main():
p201.reset()
p201.software_reset()
# internal clock 40 Mhz
p201.set_clock(Clock.CLK_40_MHz)
# internal clock 100 Mhz
p201.set_clock(Clock.CLK_100_MHz)
# channel 10 output: counter 10 gate envelop
p201.set_level_out(dict([(ct, LevelOut(TTL=True)) for ct in p201.COUNTERS]))
p201.set_output_level(dict([(ct, Level.TTL) for ct in p201.COUNTERS]))
# no 50 ohm adapter
p201.set_50ohm_adapters({})
......@@ -102,9 +102,9 @@ def main():
status = p201.get_counters_status()
if not status[counter].run:
break
msg = "\r{0} {1}".format(counter_values, latch_values)
msg = "\r{0} {1}".format(counter_values.tolist(), latch_values.tolist())
out(msg)
print("\n%{0} {1}".format(counter_values, latch_values))
print("\n{0} {1}".format(counter_values.tolist(), latch_values.tolist()))
pprint.pprint(p201.get_counters_status())
p201.relinquish_exclusive_access()
......
......@@ -19,7 +19,7 @@ except:
sys.path.append(this_dir)
from bliss.controllers import ct2
from bliss.controllers.ct2 import P201, Clock, LevelOut, CtConfig, OutputSrc
from bliss.controllers.ct2 import P201, Clock, Level, CtConfig, OutputSrc
from bliss.controllers.ct2 import CtClockSrc, CtGateSrc, CtHardStartSrc, CtHardStopSrc
......@@ -29,7 +29,7 @@ def main():
parser = argparse.ArgumentParser(description='Process some integers.')
parser.add_argument('--counter', type=int,
help='counter number', default=1)
parser.add_argument('--value', type=int, default=1000*1000,
parser.add_argument('--value', type=int, default=10000*1000,
help='count until value')
args = parser.parse_args()
......@@ -45,11 +45,11 @@ def main():
p201.reset()
p201.software_reset()
# internal clock 40 Mhz
p201.set_clock(Clock.CLK_40_MHz)
# internal clock 100 Mhz
p201.set_clock(Clock.CLK_100_MHz)
# channel 10 output: counter 10 gate envelop
p201.set_level_out({counter: LevelOut(TTL=True)})
p201.set_output_level({counter: Level.TTL})
# no 50 ohm adapter
p201.set_50ohm_adapters({})
......
......@@ -60,6 +60,12 @@ class TestP201(unittest.TestCase):
def setUp(self):
self.p201 = ct2.P201()
self.p201.disable_interrupts()
self.p201.reset()
self.p201.software_reset()
def tearDown(self):
self.p201.disable_interrupts()
self.p201.reset()
self.p201.software_reset()
......@@ -72,7 +78,7 @@ class TestP201(unittest.TestCase):
clock = self.p201.get_clock()
self.assertEqual(clock, ct2.Clock.CLK_66_66_MHz)
def test_level_out(self):
def test_output_level(self):
for c in ({9: ct2.Level.DISABLE,
10: ct2.Level.DISABLE },
{9: ct2.Level.TTL,
......@@ -83,8 +89,8 @@ class TestP201(unittest.TestCase):
10: ct2.Level.TTL },
{9: ct2.Level.NIM,
10: ct2.Level.NIM },):
self.p201.set_level_out(c)
r = self.p201.get_level_out()
self.p201.set_output_level(c)
r = self.p201.get_output_level()
self.assertEqual(c, r)
def test_output_channels_level(self):
......@@ -115,16 +121,17 @@ class TestP201(unittest.TestCase):
result = self.p201.get_output_channels_filter()
self.assertEqual(filter, result)
def test_channels_trigger_interrupts(self):
def test_channels_interrupts(self):
triggers = { 1: ct2.TriggerInterrupt(rising=True),
5: ct2.TriggerInterrupt(falling=True),
10: ct2.TriggerInterrupt(rising=True, falling=True), }
self.p201.set_channels_trigger_interrupts(triggers)
self.p201.set_channels_interrupts(triggers)
for ch in (2,3,4,6,7,8,9):
triggers[ch] = ct2.TriggerInterrupt()
result = self.p201.get_channels_trigger_interrupts()
result = self.p201.get_channels_interrupts()
self.assertEqual(triggers, result)
def test_50ohm_adapter(self):
......
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